Arteris has partnered with IC-Link by imec, imec’s design and manufacturing arm for ASICs and silicon photonics, to help speed up and simplify the development of next-generation AI and HPC chiplets and ASICs. As part of this collaboration, Arteris’ NoC IP will be integrated into IC-Link’s design ecosystem, enabling more efficient and scalable semiconductor development.
By combining IC-Link’s subsystem design expertise with Arteris’ NoC technology, the partnership aims to ease the burden of building complex chip architectures from scratch. This approach allows engineering teams to reuse proven infrastructure, reduce development effort, and bring advanced custom silicon platforms to market faster.
As AI and HPC systems continue to scale in both size and complexity, teams are under pressure to improve productivity while focusing more on innovation. Instead of repeatedly rebuilding foundational components, IC-Link offers a reusable and scalable architecture that helps streamline integration, lower design risks, and accelerate time-to-market.
At the core of modern AI and HPC systems is the need for efficient data movement across increasingly complex chips. Arteris’ technology addresses this by enabling high-performance, energy-efficient, and secure communication within semiconductor designs.
This makes it particularly valuable for applications ranging from AI data centers and edge AI devices to emerging physical AI systems.
Leadership Comments
“As semiconductor complexity continues to grow, including in AI ASICs, engineering teams increasingly need ways to reuse proven infrastructure and focus their efforts on high-performance differentiation,” said K. Charles Janac, president and CEO of Arteris. “The collaboration between IC-Link by imec and Arteris reflects a broader industry shift 
toward reusable architectures that help improve productivity, reduce risk, and accelerate innovation across AI and HPC semiconductor development.”
“IC-Link’s high-speed I/O subsystem reference design represents a significant step forward in how ASIC developers targeting high-performance computing and artificial intelligence applications address the challenges of advanced node design,” said Ozgur Gursoy, director of portfolio and strategy for ASICs at IC-Link. “With each new technology node, design teams typically face costly and time-intensive rework of their I/O subsystems. By integrating Arteris’ industry-leading network-on-chip IP, our reference design reduces risk and enables HPC and AI teams to focus on what matters most: optimizing the accelerator core.”
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