TIER IV has joined the Japan Science and Technology Agency (JST)’s Next-Generation Edge AI Semiconductor Research and Development Program, aiming to build and open-source a software-defined system-on-chip (SoC) tailored for Level 4 autonomous driving.
The Tokyo-based autonomous driving software company will develop the chip’s logic design and release both the design assets and the associated compiler toolchain to the public.
The initiative is part of a broader JST-led research effort headed by Professor Yoshihiro Kawahara at the University of Tokyo’s Graduate School of Engineering, which focuses on use-case-driven, functionally differentiated “physical AI” chip design.
TIER IV’s work will complement this by targeting end-to-end (E2E) autonomous driving AI inference, with Autoware, the world’s leading open-source autonomous driving stack, as its software foundation.
Why a new chip architecture?
While GPUs and other high-performance computing hardware have powered AI’s rapid progress, Level 4 autonomy demands always-on, real-time operation under strict power and safety constraints.
TIER IV argues that meeting these needs requires more than raw peak performance, the system must optimize performance per watt across the entire Autoware stack while improving adaptability, transparency, and verifiability.
The company plans to design an AI accelerator that can scale from low-power embedded devices (a few watts) up to in-vehicle ECUs (tens of watts), enabling flexible deployment across different vehicle platforms.
Power efficiency by design
The proposed architecture targets Transformer-based models that fuse camera images, point clouds, and other sensor data from perception through motion planning. To cut power, the design will:
- Pre-place and reuse data on-chip to minimize costly external memory transfers.
- Include dedicated compute blocks for common Transformer operations such as matrix multiplication and attention.
- Optimize for system-level efficiency with Autoware, not just peak FLOPS.
Adaptability through a software-defined SoC
Because autonomous driving AI models are evolving quickly, hardwiring a chip to a specific model risks rapid obsolescence.
TIER IV will insert the Tensor Operator Set Architecture (TOSA) as a standardized intermediate representation between AI frameworks (like PyTorch) and the hardware. In practice, model operators are converted to TOSA, then optimized and code-generated for the chip.
This loose coupling means many improvements, new model architectures, quantization schemes, or scheduling strategies can be delivered via compiler and runtime updates rather than a full silicon redesign, moving toward a truly software-defined SoC.
Transparency and an open ecosystem
Safety-critical systems demand visibility into how software maps to hardware. TIER IV will open-source the chip’s logic design along with its compiler and toolchain, allowing semiconductor vendors and developers to inspect, modify, and extend the architecture for their own platforms, performance targets, and power budgets.
The goal is to extend Autoware’s open-source model down to the silicon layer, creating an ecosystem where chipmakers can leverage TIER IV’s platform technologies to accelerate commercialization of Level 4 SoCs without being locked into closed, proprietary stacks.
Verifiability for safety assurance
Executing AI on silicon involves multiple transformations, format conversion, optimization, quantization, rounding that can introduce numerical differences.
To address this, TIER IV will structure the compilation flow around TOSA’s well-defined operator specs and apply formal verification techniques to selected transformations.
This approach aims to mathematically verify numerical consistency and adherence to error tolerances before and after compilation, providing a traceable, auditable path from model to on-chip execution. The result is an execution environment where correctness can be checked, not just assumed, critical for Level 4 autonomy.
What this means for the industry
By open-sourcing both the AI chip design and its toolchain, TIER IV is betting that an open, software-defined hardware stack will speed up innovation and reduce barriers for semiconductor companies entering the autonomous driving market.
If successful, the program could help shift the industry from closed, vertically integrated SoCs toward modular, verifiable platforms that evolve alongside AI models, much as Autoware has done for autonomous driving software.
Leadership Comments
“Advances in AI have been accelerated by powerful computing platforms, including GPUs, which have enabled rapid progress across the industry,” said Shinpei Kato, founder and CEO of TIER IV. “As Level 4 autonomous driving moves toward broader deployment, we believe the next step is to complement these platforms with computing architectures designed for real-world and real-time requirements. Through this initiative, we are introducing a software-defined and open approach to AI chip design that combines power efficiency, adaptability, transparency and verifiability.”
“In particular, the ability to understand how an AI model is transformed for execution and 
to verify the correctness of that processing will be increasingly important as autonomous driving systems are deployed in safety-critical environments. By extending the open-source philosophy behind Autoware from software to AI chip design and related toolchains, we aim to create an open ecosystem in which automakers, semiconductor manufacturers and developers can build upon the technology and continue advancing their own systems. This represents an important step toward a scalable, adaptable and reliable computing foundation for Level 4 autonomous driving,” said Shinpei.
“In physical AI applications such as robotics and autonomous driving, GPU power consumption has long been a major bottleneck for deployment on battery-powered devices,” said Professor Yoshihiro Kawahara of Graduate School of Engineering, The University of Tokyo. “This project aims to fundamentally overcome this constraint through a functionally differentiated chip design backward-mapped from specific use cases. I look forward to TIER IV developing chips responsible for high-level decision-making – specifically, the high-level behavioral layer that handles the thinking process essential for end-to-end physical AI and autonomous driving. As the leading force behind Autoware, the global standard open-source software for autonomous driving, TIER IV is democratizing design, with an approach spanning application requirements to hardware. This enables applied researchers to shape their ideal semiconductors. This initiative, supported by an open ecosystem, has the potential to lay the foundations for a steady stream of Japanese startups creating high-value semiconductors.”
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