TYLsemi™ has emerged from stealth with an oversubscribed $43 million early-stage funding round, positioning itself to accelerate the next wave of AI infrastructure built on chiplet-based architectures.
The round was led by Matter Venture Partners, with participation from Viola Ventures, GHOVC, Egis Technology, and several strategic investors from across the semiconductor and AI infrastructure ecosystem.
Founded by industry veterans Mohit Gupta and Sunil Bhardwaj, who have held leadership roles at Alphawave (acquired by Qualcomm), SiFive, Cadence Design Systems, and Rambus. TYLsemi is aiming to address a growing gap in the AI hardware stack.
At the core of its strategy is a production-ready, standards-based chiplet platform that spans IO, power delivery, and memory. The company combines this portfolio with custom silicon design, system integration, and supply chain ownership to offer customers a faster, lower-risk path from architecture to deployment.
The timing aligns with a broader industry shift. As AI workloads scale, traditional monolithic chip designs are hitting physical and performance limits. In response, chipmakers are moving toward modular, multi-die architectures enabled by advances in packaging and interconnect standards such as UCIe.
TYLsemi’s approach centers on making chiplet-based systems practical at scale. Its reusable portfolio allows customers to deploy chiplets as standalone components or as building blocks for fully customized silicon solutions using leading foundry and packaging technologies.
The company’s initial product lineup reflects this modular strategy:
- IO™ is a family of connectivity chiplets designed for high-bandwidth, standards-based communication across AI systems. It supports interfaces such as PCIe, ESUN, and UALink, with a roadmap that includes co-packaged optics for next-generation rack-scale architectures.
- Power™ introduces an intelligent in-package power delivery solution for XPUs. Built around an integrated voltage regulator chiplet, it is designed to improve efficiency and optimize system-level power management.
- Mem™ will focus on memory connectivity for advanced AI systems, with further details expected as the roadmap evolves.
- ForgeSM serves as the company’s end-to-end platform for custom silicon development. It enables customers to design XPUs, compute elements, and fabric architectures, combining TYLsemi’s chiplets with IP, foundry access, advanced packaging, and production capabilities.
With its integrated approach, TYLsemi is positioning itself as a key enabler of scalable, chiplet-driven AI infrastructure, an area increasingly seen as critical to meeting the performance, power, and flexibility demands of next-generation computing.
Leadership Comment
“The AI accelerator market is on track to reach $604 billion by 2033 and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment,” said Mohit Gupta, Founder and CEO of TYLsemi. “At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-
die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon.”
“AI infrastructure is undergoing a fundamental shift toward modular, chiplet-based design, but the ecosystem has not kept pace,” said Jim Handy, General Director at Objective Analysis. “This represents a significant opportunity for a company such as TYLsemi that can deliver pre-validated, standards-based silicon to accelerate AI infrastructure silicon deployment.”
TYL.IO and TYL.Power chiplet samples will be available to qualified customers in 2027 in partnership with TSMC; TYLsemi is now engaging lead customers for its TYL.Forge platform.
