Rambus has unveiled its Rambus PCIe 7.0 Switch IP with Time Division Multiplexing (TDM), the latest addition to its high-speed interconnect lineup. It’s built to tackle the exploding bandwidth, latency, and scalability needs of AI, cloud, and HPC systems.
AI setups are getting bigger and more complex every day, making it tough for designers to shuttle huge data loads between CPUs, GPUs, accelerators, and NVMe storage.
This new PCIe 7.0 switch with TDM steps in by making PCIe links more flexible and efficient. It supports disaggregated compute and pooled architectures without sacrificing low latency or predictable performance.
Optimized for AI and Data Center SoCs
Running on the PCIe 7.0 spec, this switch IP is tailored for cutting-edge AI and data center SoCs that demand massive bandwidth density, smart traffic handling, and easy scaling.
The TDM feature lets designers schedule and multiplex traffic smartly across shared links, squeezing the most out of the fabric for everything from massive AI training runs to real-time inference and data shuffling.
Bolsters Rambus’ PCIe Portfolio
It slots right into advanced ASIC designs and pairs perfectly with Rambus’ full PCIe 7.0 suite, controllers, retimers, debug tools, and more.
All this helps customers hit the market faster while meeting the intense power, performance, and reliability bars of today’s AI infrastructure.
This launch cements Rambus’ dominance in high-speed interface IP, showing their dedication to innovative interconnects that crack the toughest challenges in AI, cloud, and HPC.
Leadership Comment
“The acceleration of AI is fundamentally reshaping system architectures, and it’s no longer sufficient to simply add more lanes or more endpoints,” said Simon Blake-Wilson, senior vice president and general manager of Silicon IP at Rambus. “With our PCIe 7.0 Switch IP with TDM, Rambus is giving system architects a new degree of freedom to scale bandwidth efficiently and deterministically, while reducing complexity and improving overall system utilization. This is a critical enabler for scale up and scale out of the next wave of advanced AI clusters and HPC networks.”
“AI infrastructure is increasingly defined by how efficiently data can move between heterogeneous compute and memory resources,” said Jeff Janukowicz, VP, Semiconductors and Enabling Technologies. “Advanced PCIe switching technologies that improve link utilization and enable flexible traffic orchestration will be key to building scalable, cost?effective AI platforms as next?generation interconnect technology evolves.”
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