Defacto Technologies, a provider of EDA solutions for SoC design, has announced upgradation of SoC Compiler software to automate front-end SoC integration procedures for complex RISC-V architecture.
Addressing Growing Complexity of RISC-V SoC Designs
This innovation is intended to solve the growing complexity and scalability difficulties of RISC-V SoC designs, as the open-source RISC-V architecture becomes more widely employed in embedded applications. While RISC-V provides freedom and openness, the RTL design process for RISC-V SoCs is produced and optimized using internal solutions (via proprietary scripts) and is still mostly manual, especially for multicore processors and large-scale designs.
Despite internal scripting and tools, current front-end integration methods have structural inefficiencies, such as a lack of design reusability because designs are often designed for unique configurations and are not portable between projects.
Building a complicated SoC design project typically consists of many essential steps: selecting and configuring IPs, interconnecting them, generating the appropriate design files for implementation and verification procedures, and completing the validation stage.
This entire process is repeated for each new project, resulting in time loss and inefficiencies as teams must recreate design integration from the beginning.
From IP selection and configuration to connection and file production, the process is primarily manual. Iterating through big RISC-V SoCs is time-consuming and error-prone.
Managing the gap between internal IP cores and updated open-source IPs is a difficult task. Differences between open-source RISC-V IPs (e.g., GitHub-based) and customized internal versions necessitate attention and ongoing revisions.
Modifications to one cause changes to the other, and teams lose time and energy coordinating everything.
Defacto’s SoC Compiler enables users to easily explore and generate various SoC configurations, ranging from RTL to design collaterals, based on user specifications, with minimal manual parametrization and interaction.
The company’s new software provides extensive RTL linting tests for VHDL, Verilog, and System Verilog languages. Structural checks include connection, clock tree, and interface checks, among others.
The Defacto software provides a comprehensive set of features meant to enhance SoC integration pre-synthesis, including an optimised and up-to-date library of configurable RISC-V IP cores, as well as the option for users to incorporate their own bespoke IPs.
Designers can use Python or Tcl APIs to accelerate development by leveraging a range of SoC design templates, while built-in testing tools ensure quality through IP core linting tests and coherency checks across various design views.
The tool is fully compatible with all RTL languages, including Verilog, VHDL, and SystemVerilog, and provides significant customization possibilities to meet a variety of project requirements.
In addition, RTL rearrangement features like Feedthrough management let designers to optimize Power, Performance, and Area (PPA). They assist in adjusting the design to meet physical constraints by refining structures such as deleting long loops, loopbacks, and redundant ports.
These advancements enable aggressive die size reduction while also considerably improving the reusability of designs and IP across projects.
The tool also makes it easier to integrate design modifications, which speeds up iteration and improves team coordination.
Defacto’s SoC Compiler simplifies and speeds up RISC-V design configuration compared to manual techniques.
Managing RISC-V SoC Designs Efficiently
Engineering teams can generate and manage RISC-V-based SoC designs more efficiently, resulting in faster design cycles and shorter turnaround times.
They can also devote more attention to debugging, optimizations, and high-value design tasks, while benefiting from improved IP and architecture reusability across projects.
This technique is thought to better correlate with the growing requirement for scalable and automated design methodologies as RISC-V expands its presence in high-performance embedded applications.
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