Semidynamics introduced its groundbreaking ‘All-In-One AI’ IP tailored for highly advanced AI chips and cutting-edge algorithms like transformers.
Traditionally, AI chip developers have relied on integrating distinct IP blocks alongside the system CPU to meet the escalating AI requirements.
However, Semidynamics has innovatively devised a unified solution that merges RISC-V, vector, tensor, and Gazzillion technologies, simplifying the programming of AI chips and enabling seamless scalability to meet any processing demands.
The demand for AI is continuously growing, leading to an increase in data volume and processing requirements. The current approach involves integrating more specialized functional blocks to handle this demand.
The CPU assigns specific tasks to gpGPUs (general purpose Graphical Processor Units) and NPUs (Neural Processor Units), facilitating communication between these units. However, transferring data between these blocks results in significant latency issues.
Additionally, programming becomes complex with three different types of IP blocks, each with its own instruction set and tool chains.
Furthermore, non-programmable NPU blocks may become outdated even before they are implemented in silicon due to the rapid evolution of AI algorithms.
Consequently, an AI chip designed today may be obsolete by the time it is manufactured in 2027, as software advancements leaves behind hardware development.
Roger Espasa, CEO of Semidynamics, said, “The current AI chip configuration is inelegant with typically three different IP vendors and three tool chains, with poor PPA (Power Performance Area) and is increasingly hard to adapt to new algorithms. For example, they cannot handle such as an AI algorithm called a transformer but our All-in-One AI IP is ideal for this. We have created a completely new approach that is easy to program as there is just the RISC-V instruction set and a single development environment. Integrating the various blocks into one RISC-V AI processing element means that new AI algorithms can easily deployed without worrying about where to distribute which workload. The data is in the vector registers and can be used by the vector unit or the tensor unit with each part simply waiting in turn to access the same location as needed. Thus, there is zero communication latency and minimized caches that lead to optimized PPA but, most importantly, it easily scales to meet greater processing and data handling requirements.”
Semidynamics has amalgamated four of its cutting-edge IPs to create a unified solution known as the ‘All-In-One AI’ IP processing element.
This ‘All-In-One AI’ IP by Semidynamics feature a fully customizable RISC-V 64-bit core, Vector Units (acting as the gpGPUs), a Tensor Unit (serving as the NPUs), and the Gazzillion® Unit to efficiently manage vast amounts of data from any location in the memory without encountering cache misses.
Consequently, there is a single IP provider, a single RISC-V instruction set, and a single tool chain, streamlining the implementation process significantly and accelerating it with reduced risks. Multiple instances of these new processing elements can be integrated on a single chip to develop a next-generation, high-performance AI chip that caters to the requirements of various applications.
Roger Espasa concluded, “We have established a completely new way to architect ever more powerful chips that we believe will enable AI to overcome the shortcomings of the current state-of-the-art designs. Our revolutionary, integrated, All-In-One AI processing elements create a scalable solution that will be at the heart of a whole new generation of ultra-powerful AI chips which will be accessible to everyone. By using our new Configurator tool, they can create the appropriate balance of Tensor and Vector units with RISC-V control capabilities in the processing element.
“The RISC-V core inside our All-In-One AI IP provides the ‘intelligence’ to adapt to today’s most complex AI algorithms and even to algorithms that have not been invented yet. The Tensor provides the sheer matrix multiply capability for convolutions, while the Vector unit, with its fully general programmability, can tackle any of today’s activation layers as well as anything the AI software community can dream of in the future. Having an All-In-One processing element that is simple and yet repeatable solves the scalability problem so our customers can scale from a 1/4 TOPS to hundreds of TOPS by using as many processing elements as needed on the chip. In addition, our IP remains fully customisable to enable companies to create unique solutions rather than using standard off-the-shelf chips.”
