Sondrel declared that its exclusive intellectual property(IP) was available for license. This begins with a series of IP blocks for general SoC management, which oversees power domain handling, clock and reset control, and device startup. The PMU (Power Management Unit), URG (Universal Reset Generator), and UCG (Universal Clock Generator) are the three parts of the SoC Management Suite.
The Power Management Unit (PMU) is used for:
- Managing the start-up of the SoC and bringing the SoC out of reset.
- Providing software control to allow any switchable digital domains to be powered up and down.
- Providing software with control over the reset tree (once start-up is complete).
- Managing system faults (including taking mitigating action as required and acting as the Error Detection Unit).
- Generating the system response to functional safety faults detected in the system. Such as putting the system into ‘Safe-Mode’.
Using Sondrel’s Power Down Controller Interface control bus, the PMU can communicate with a URG to manage the resets.
On-chip reset management is coordinated by the Universal Reset Generator (URG), a SoC IP. Reset-tree management for the growing complexity of logic within a SoC is the primary goal of this IP. It is designed to be scalable and lightweight in order to work with various SoC types. While a multi-power-domain SoC or implementation that requires more dispersed reset control may have numerous instances based on the reset tree management requirements, a conventional SoC would use at least one URG IP instance.
A single, generically configurable block that supports the proper sequencing of system-wide resets is the aim of URG.
Events that would change the state of the resets can come from several sources:
- A hardware trigger. Examples include: a system reset pin, a watchdog timer IP, a security IP, a CPU exception flag
- A software-driven event. i.e. a driver deciding that IP is in an unknown state.
- The Power Management Unit, which must manage resets in tandem with power island voltage controls to facilitate power state transitions.
On-chip clock management coordination is handled by the Universal Clock Generator (UCG), a SoC IP. It is designed to be scalable and lightweight so that it may be applied in any scenario.
It Supports:
- Multiple clock sources and references as input to a generic crossbar.
- Up to 128 clocking channels which can be independently software configured.
- Clock dividers on each channel and a clock enable (glitch-free implementations).
- Observation clocking points.
- DFT (Design For Test) control of clock outputs.
- Safety mechanisms such as detecting if a default clock has failed and indicating the fault to the system.
Key Comments
Oliver Jones, Sondrel’s CEO, said, “For years, we have been creating IP blocks for our internal use when we design custom chips. We are now making these available for licensing by third parties. They are silicon proven as we have already successfully used them in designs for our customers. We had to create these IP blocks as there was nothing commercially available to deliver the functions and performance that we required for the advanced ultra-complex custom chips that we design. Some are slightly unusual but that is the very reason why we created them. If we needed them for a design then others will too.”
For Further Info on SoC Management Suite IP: CLICK HERE
