Microchip Technology has unveiled its latest generation of Switchtec Gen 6 PCIe switches in response to the increasing need for faster data transmission and reduced latency being driven by artificial intelligence (AI) workloads and high-performance computing (HPC) applications.
The Switchtec Gen 6 family, the first PCIe Gen 6 switches in the industry to be produced utilizing a 3 nm process, is intended to provide reduced power consumption and handle up to 160 lanes for high-density AI system communication.
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Underutilization and wasted computation cycles resulted from bandwidth bottlenecks caused by earlier PCIe generations when data moved between CPUs, GPUs, memory, and storage.
By doubling PCIe 5.0’s capacity to 64 GT/s (giga transactions per second) per lane, PCIe 6.0 creates the data pipeline required to continuously supply the most powerful AI accelerators.
Switchtec Gen 6 PCIe switches are made to help data center architects scale to the potential of next-generation AI and cloud architecture by enabling high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators, and storage devices.
In order to minimize signal loss and preserve the low latency needed by AI fabrics, the switches function as a high-performance interconnect, enabling easier, more straightforward interactions between GPUs in a server rack.
Additionally, the PCIe 6.0 standard adds dynamic resource allocation, a lightweight Forward Error Correction (FEC) system, and Flow Control Unit (FLIT) mode.
Particularly for short packets, which are typical in AI workloads, these modifications improve the efficiency and reliability of data delivery. Lower effective latency and increased overall throughput are the results of these upgrades.
Switchtec Gen 6 PCIe switches have ten stacks and twentxy ports, each of which has a hot-plug and surprise-plug controller.
Additionally, Switchtec Gen 6 PCIe switches provides multicast for one-to-many data distribution inside a single domain and NTB (Non-Transparent Bridging) for connecting and isolating many host domains.
The switches have a large range of I/O interfaces, an integrated MIPS CPU with bifurcation choices at x8 and x16, and sophisticated error containment, diagnostics, and debug capabilities. Four input clocks per PCIe stack serve as the foundation for input and output reference clocks.
Leadership Comments
“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organized as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data center solutions business unit. “By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy efficient switch we’ve ever produced.”
Development Tools
The Switchtec Gen 6 PCIe Switch family is supported by Microchip’s ChipLink diagnostic tools, offering comprehensive debug, diagnostics, configuration and analysis through an intuitive graphical user interface (GUI).
ChipLink connects via in-band PCIe or sideband signals such as UART, TWI and EJTAG, enabling flexible, efficient monitoring and troubleshooting throughout design and deployment.
The Switchtec Gen 6 PCIe switches are also supported by the PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit with multiple interfaces.
Pricing and Availability
Switchtec Gen 6 PCIe switches are available for sampling to qualified customers. Contact a Microchip sales representative or authorized worldwide distributor for more information.
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