Cadence introduced the first DDR5 12.8 Gbps MRDIMM Gen2 memory IP system based on the TSMC N3 process, addressing the requirement for increased memory bandwidth for AI processing demands in enterprise and data center applications, including AI in the cloud.
The new 12.8 Gbps DDR5 MRDIMM IP features a new high-performance, scalable, and adaptive architecture built on Cadence’s well-established and successful DDR5 and GDDR6 product lines.
The Gen2 DDR5 IP includes a PHY and a high-performance controller, forming a full memory subsystem. The concept is proven in hardware using the most recent MRDIMMs (Gen2), resulting in a best-in-class data throughput of 12.8 Gbps, which doubles the bandwidth of existing DDR5 6400 Mbps DRAM components.
The DDR5 IP memory subsystem is based on Cadence’s silicon-proven, high-performance architecture, ultra-low latency encryption, and industry-leading RAS capabilities.
The DDR5 MRDIMM Gen2 IP is intended to accommodate advanced SoCs and chiplets through variable floorplan design options, and the new architecture allows for fine-tuning of power and performance based on unique application requirements.
The DDR5 controller and PHY have been verified with Cadence’s Verification IP (VIP) for DDR to provide rapid IP and SoC verification closure.
Leadership Comments
“The Cadence DDR5 IP portfolio, together with Micron’s industry-leading 1? (1-gamma)-based DRAM, meets the increasing demand for higher memory bandwidth, density and reliability for AI processing workloads. These memory enhancements are pivotal in enabling the next generation AI/ML and HPC applications in data centre and enterprise environments,” said Praveen Vaidyanathan, vice president and general manager of Micron’s Data Center Products.
Data centre and enterprise applications stand to gain a significant performance advantage from Cadence’s DDR5 12.8 Gbps MRDIMM IP system, as evidenced by large customers turning to Cadence to deliver this innovative technology,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “This new leading-edge memory IP system raises the bar and establishes a roadmap that future-proofs our customers’ next-generation SoC and chiplet products for generations to come.”
For Further Info, CLICK HERE
