Synopsys has announced new advancements across its hardware-assisted verification (HAV) portfolio, introducing fresh platforms and capabilities designed to meet the surging demand for AI chip verification from data centers to the edge.
Powered by software-defined innovation, Synopsys HAV solutions push new boundaries for performance, scalability, and functionality, helping designers verify the world’s most complex multi-die and AI chips under growing design and time-to-market pressures.
As AI models continue to grow doubling in size roughly every four months and interface data rates double every three years, verification challenges are becoming exponentially tougher.
At the same time, edge AI systems are targeting higher throughput, lower latency, and greater power efficiency, which all add to the design and validation workload.
Keeping pace requires verification platforms that can handle massive workloads, cover diverse applications, and run quadrillions of verification cycles to ensure first-time silicon success and seamless integration across heterogeneous AI systems.
Among the latest updates:
- Performance and capacity breakthroughs for the AI era: Synopsys has introduced new software-defined improvements across its ZeBu and HAPS platforms. The ZeBu Server 5 now delivers industry-leading capacity for large, data center-class designs such as AI training and inference engines, GPUs, and networking workloads. Meanwhile, modular HAV updates for HAPS enhance compute, storage, and bring-up for the industry’s largest prototypes.
- New HAPS and ZeBu systems: The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems double the capacity of previous six-FPGA platforms. Built around AMD’s Versal Premium VP1902 adaptive SoCs, they offer “EP-Ready Hardware” for seamless transitions between prototyping and emulation. Synopsys also rolled out the compact HAPS-200 1 FPGA, a desktop-ready platform for IP verification and early software development.
- Software-defined HAV capabilities for lasting value: Continuous software updates deliver ongoing performance improvements, stronger debug productivity, and new functionality across installed systems. Synopsys also introduced Hardware-Assisted Test Solutions that automate stress testing across processors, memory, and I/O subsystems. These tools help teams analyze full-system coherence and behavior under realistic workloads long before silicon arrives. For mixed-signal and system-level projects, Real-Number Models (RNM) enable scalable analog abstraction in digital flows. And for safety-critical designs, new fault emulation tools support scalable fault injection and analysis across multiple verification stages.
Leadership Comments
“AI-driven systems are scaling in complexity, and verification must scale with them,” said Salil Raje, Senior Vice President and General Manager of AMD’s Adaptive and Embedded Computing Group. “Hardware-assisted verification isn’t optional anymore — it’s essential to achieving tight schedules and silicon readiness. FPGA-based emulation and prototyping accelerate system bring-up and early software development. Our collaboration with Synopsys focuses exactly on that, optimizing Synopsys ZeBu with the AMD Vivado software stack and leveraging AMD EPYC processors for faster compile times and more accurate system modeling.”
Ravi Subramanian, Chief Product Management Officer at Synopsys, echoed this sentiment: “As AI continues to redefine industries, it’s critical to validate early that workloads are performing to specification on the silicon under design. Our software-defined, hardware-assisted verification solutions are a force multiplier that help teams scale verification productivity and meet the industry’s growing pre-silicon demands.”
The new software-defined enhancements are now rolling out across the Synopsys HAV portfolio. The HAPS-200 12 FPGA and HAPS-200 1 FPGA platforms are available today, while the ZeBu-200 12 FPGA system will be available in Q3 2026.
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