We’re focused on delivering value through intelligent integration, not chasing the costly race to advanced logic nodes like 3nm or 2nm,” asserts Suman Narayan, CEO of Cyient Semiconductors. In this exclusive Volt-Age interview, Narayan spotlights the company’s $100 million commitment and shares an inside look at Cyient Semiconductor’s collaborative strategies with policymakers to drive innovation. Below are edited excerpts from this insightful discussion.
Cyient has been in the headlines for its latest announcement to establish a dedicated semiconductor subsidiary with the investment it mends that is $100 million – it is where my maiden question is – is it now that we will finally have a ‘sand to silicon’ reality?
The 100 million dollar commitment reflects our ambition to make India a formidable design hub and build a semiconductor ecosystem.
We’re not building a fab rather our focus is to build a world-class design system and an ecosystem that helps us to create semiconductor design.
We believe that India’s competitive advantages in the design linked initiatives with strong Government push. We also feel this is the salient time to launch innovative semiconductors from India to the world.
Major semiconductor companies have lately established their OSAT in India while other few are revving – up for chip design facilities in India. In the most of the cases partnerships, exchanging “tech know-how” has been pivotal, how do Cyient Semiconductors strategizes to move forward?
The need of the hour is for diversifying the supply chains and Cyient Semiconductors is set to tap the potential as many companies are already setting up their OSATs in India.
And also because of geopolitical issues, the whole supply chain has become more complex therefore it has become eminent that we have an US, Europe and China based supply chain.
Here in Cyient Semiconductors, we have good strategic symbiotic partnerships with the IP vendors. Maybe it be an OSAT, foundry or IP companies we can build a credible chip quickly for our customers.
To complement our vigorous strategic moves, lately we’ve on boarded semiconductor veterans like Mohandass Sivakumar from Amkor Technology and Derek D’Antilio, CFO from Allegro Microsystemsn our advisory board. This shall add an impetus and bolster the supply chain.
We’re working through our partners and our board of advisors to have multiple supply chains. Here the good news is, I’ve done all of this in my past, so it should help us to move faster in the current environment.
Turnkey and design service models are pretty challenging for Chip Companies – in a time where managing supply chain disruptions, getting cost, quality parity, and building coordinating multidisciplinary teams seems to be an unforgiving challenge?
If one looks at why it is complex then one has to dive in to the complexities of evolving design in low nanometer silicon which is less than maybe 28nm type of silicon. Here it becomes not only complex but also expensive.
Today what do our customers want? They want fast execution, which means that the chip comes out working the first time.
Does it happen all the time? Absolutely not so you have to do a metal change, but this is an expensive mass that you’re talking in less than 28nm, so we have to make sure that the design that we’re doing works at the first time.
But if you look at chips maybe over 40nm, you can push your cycle time because the cost of doing this development is not that expensive.
The other complexity that I mentioned was the supply chain constraints.
Balancing out the design where you’re doing the design, assembly and test and figuring out where actually you want to focus. For say in power, analog mix signal, MCU so here the complexity comes in the recipe, the complexity comes in the time to market the complexity comes in the supply chain as well.
What process nodes will you operating on and also are you eyeing on advanced nodes like 3nm and 2nm, or the nascent sub-2nm technologies?
We’re currently focused on mature nodes like 40nm, 65nm etc. These nodes are optimal for analog mixed signal and power design. These process nodes are proven reliability and cost efficiency for our target markets.
We’re not chasing advanced logic nodes like 3nm or 2nm because our value lies in the intelligent integration, not in the bleeding edge scaling applications which are super expensive and require huge R&D.
We remain open to heterogeneous integration if it aligns with the customer needs. If you know you could have multiple die on the same chip with multiple process nodes and easily integrate them into one SOC type solution.
While with the growth of GenAI, Automotive computing etc. advanced multichip packaging, advanced packaging represents a radical shift in the semiconductor industry, what packaging types are you opting today?
The growth of GenAI and the automotive compute is primarily about providing more power to the GenAI chips and the automotive computing chips.
We’re actually working on Multi-die lead frame packages that suit the power and analog domains, but a lot of these packages are evitable standard packages.
Today we’re exploring substrate based packaging and co-design packaging for the data center applications. Advanced packaging like 2.5D and all the chiplette-based systems our in our roadmap for the compute intensive applications but will primarily be demand driven.
Is Cyient Semiconductors engaging with policymakers to shape regulatory frameworks around chip design, IP, or domestic sourcing?
We’re in active discussions with India Semiconductor Mission (ISM) and a lot of state level authorities.
We predominantly want to focus on IP development, domestic sourcing and enabling a local design ecosystem.
Like some of the other countries have done, we believe that India’s policies will help us support the indigenous chip development in not just manufacturing but also making sure that we are developing a strong design ecosystem because the talent in India is just amazing for us to leverage and build some brilliant chips over the next couple of years.
Are there plans for additional funding rounds or exploring IPO opportunities for Cyient Semiconductors in the future?
The capital structure for the semiconductor business is very different from standard other businesses, So we have to make sure that we have the right capital for driving the R&D, relationship with our partners.
For now, IP is not an immediate goal, but we’re really building a mindset in the company that that is structured, scalable and performance focused.
Are you planning any partnerships with Industry bodies, academic institutions, or skilling platforms to build a future-ready workforce?
There’s a ton of talent in India and our focus is really to work with the IIIT Hyderabad and many more leading varsities and institutions.
We’re also planning to engage with skilling platforms and curriculums. We also plan to create industry relevant programs while focusing on analog design verification systems engineering.
We need to make sure that the future is ready with the right talent. Over the next couple of years, we continue to grow to understand about semiconductors.
What will be the USP of Cyient Semiconductors when comparing to global magnets emerging and dedicated to this sector?
What do our customers want, they want working silicon. They also want high levels of integration, smaller form factor, lower power and smaller area and really reduce time to market.
If you look at a lot of our customers we give them an option to also integrate their differentiated IPs so they have a differentiated product in the end market. So the higher levels of integrations the smaller form factors are really what drive us to be different from the providers.
The multinational companies that provide silicon today have excellent talent in the analog mixed signal space. We’ve taped out around 450+ and we built a plethora of IP blocks. You can think of these as LEGO blocks, building very fast to shorten the time to market.
Moving forward our pivotal focus shall be on high voltage electronics and their applications.
Are you capable of doing designs in High Voltage Process?
Everybody has a different definition of voltage, so first let’s understand what is Low Voltage, Mid Voltage and High Voltage?
I look at the low voltage running maybe less than 1 to about 3V to 5V that’s really low voltage, whereas, mid voltage you’re running between maybe 5V to 24V and in high voltage, you’re running between 24V to really maybe closer to 150V and then you’ve got a break. And then we’ve got very high voltage, which is a 600V sort of designs.
Our focus is primarily around the 100V to 120V type designs, which is really a scope for the custom analog mixing of Power ICs. With the high voltage VCD process, we’re engaging with a lot of foundries. According to typical profile of your customers and end market demand primarily we want to tap data center infrastructure with our power delivery thermals which is also a big problem for the data infrastructure market.
If you see the growth in the industrial automation space, Cyient Semiconductors sees a lot of opportunity on power reduction. Alongside smart energy, primarily around meters and EV chargers, we see a lot of integration happening and also on the robotic space.
Are there any early client engagements or design wins that you can share to illustrate market traction?
We have some good applications in smart metering that we’ve got good traction. Alongside Cyient Semiconductors have some great portfolio catering the medical industry. We’re making great strides towards ASIC.
Now we’ve got an eight week start or a nine week start if you count this week, so we have a lot of work to do to continue to grow that pipeline and we continue to hire sales to help us, you know, improve that pipeline for design.
Lastly a personal question, what Suman be found doing while not chairing his CEO responsibilities. And what is your one suggestion you want to add up for the new talent pool and aspiring chaps entering the semi biz?
Besides semiconductor technology, I hardly engage in other gigs. But I do enjoy spending long hikes with my family and my dog so that’s kind of our decompression towards the end of the day.
On the other hand, I would suggest people entering the semiconductor business or sector; just remember Malcom Gladwell’s book, Outliers stating “10,000 Hours Rule” – so learn as much as you can and be like the artisan in your craft.
This rule shall help one to focus on and become excellent in what they do and I’d say that the first five years have a growth mindset be a sponge, you know, learn as much as you can and focus on being ethical and humble because a semiconductor market is a tough market, but if you’re focused on being humble, have a growth mindset, it’ll get you a long way in your semiconductor career.
