An Advanced modeling Process for AI chip designs was announced by Sondrel. This is applied to each phase of the design of a chip in order to “prove” that the design complies with specifications (Functional Verification) and that it performs as intended (Performance Verification).
AI at The Edge and The Growing Power Consumption
AI power consumption is a popular issue; according to some forecasts, data center power usage might increase global energy requirements. With artificial intelligence (AI) becoming more and more prevalent in devices, there is a clear need to analyze data as much as possible before transmitting it to the cloud, a practice known as AI at the Edge.
In order to achieve this effectively, it is necessary to minimize the power consumption of these computationally demanding devices, which calls for the use of sophisticated nodes to meet the goals.
Sondrel is currently working on 3nm designs and has always specialized in designing at the cutting edge of chip technology. Sophisticated manufacturing technologies allow power consumption to be limited while providing the performance that these incredibly complex custom chips require from their billions of transistors.
The Process’s ability to identify and map the behavioral interactions between processors and memory to the remaining chip functions is a crucial component. With this knowledge, Sondrel’s designers can monitor the chip’s performance and adjust the design to attain the necessary ratio of Power, Performance, and Area.
Key Comments
Paul Martin, Sondrel’s Global Field Engineering Director, explained, “AI chips are extremely complex to design because of the huge amounts of data that have to flow round them between the heterogeneous processors, IO and the memory. There cannot be periods when the processors are stalled waiting for data, which is made more complicated when the chip has several different types of processors each with different data traffic requirements. This new Process enables us to analyse and balance the dataflow through the chip whilst executing the software workloads on the AI chip.”
“This uses accurate, cycle-based, system performance modeling early in the design cycle in advance of RTL development, enabling us to check that the design will meet its specification. The Process then continually evolves as RTL and eventually silicon becomes available to validate the design performs as specified. To accelerate the design process, we base the design on our Architecting the Future platform to ensure that we have a reliable, predictable path to market. This means we are reusing pre-verified design elements in the Process that constrain the solution space whilst ensuring high confidence in the integration of those elements, which also reduces risk and time to market, adds Paul.”
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