SignatureIP launches its new iNoCulator™ NoC configuration tool with a free trial period of two weeks for customers.
The NoC (Network on Chip) is the backbone of a chip that provides the interconnect infrastructure between the key processing elements.
SignatureIP’s new Network on Chip tool enables users to rapidly find the optimal NoC configuration to reduce costs and speed up time to market, and the company believes that it is the fastest on the market due to innovative and intelligent algorithms.
Purna Mohanty, SignatureIP’s CEO, explained, “This try before you buy offer will enable engineers to see for themselves just how easy it is to design a NoC with our tool and hence our tagline of NoC in a SNAP™. Our whole philosophy is to empower the engineer to quickly experiment with different configurations of the SoC architecture and then simulate them in real time to measure throughput and latency so that they can optimise the design at the top level. Thus, the System Architect sets the target Power, Performance, Areas and Timings into iNoCulator, and it creates possible topologies that can be easily and quickly tweaked to find the optimal solution. It really is a case of tell the tool what you want, and it does all the hard routine work that used to take skilled engineers a long time.”
In addition to the ‘Try Before You Buy’ offer, customers can then take a subscription license on an annual basis that can be used for the interactive architectural exploration of any number of designs. It provides full access to all aspects of the tool and enables downloading the RTL of the final design for a fee per design download.
At all stages, and especially during the initial trial, SignatureIP provides extensive support to help customers understand the full range of available features that enable the creation of an optimised Network on Chip.
iNoCulator enables interactive whiteboard editing of the Network on Chip topology through connection of initiators, routers and endpoints, and easy configuration.
It supports on-the-fly instant simulation of bandwidth and latency, and estimation of power and area. iNoCulator provides pushbutton RTL generation with targets to an SoC design flow or to an FPGA emulation flow.
The iNoCulator EDA tool is processor agnostic so that it can be used with, for example, Arm® or RISC-V processors and can connect many other on-chip IP blocks such as PCIe, CXL, and AI acceleration. This capability enables designers to create complex, high-performance heterogeneous SoCs that can support a wide range of applications, from data center acceleration to edge AI devices.
Intelligence built in
A key part of the ease of use is that SignatureIP has built-in intelligent algorithms to automate and speed up many of the processes involved in scenario building that would have otherwise required manual configuration.
“This enables the tool to automatically try many different Network on Chip layouts to find the ones that best suit to parameters set at the start,” added Mohanty. “This not only speeds up what used to be a complex and slow process with a lot of human inputs to optimise, resulting in a faster time to market and revenue, but also reduces risk. We believe that this makes iNoCulator the fastest NoC configuration tool on the market at the moment.”
Technical details
Supports non-coherent Network on Chip and can be configured as ring, mesh, concentrated mesh or torus topologies. It also has support for popular interface protocols (AXI, AHB, APB, SRAM) and multiple bus widths. The multiple clocking schemes include GALS, and the power control has power island generation and UPF output. It creates a layered, scalable physically-aware network.
For more information about SignatureIP products and for a free trial, please visit https://www.signatureip.ai/
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