Marvell Technology is reportedly deepening its collaboration with TSMC to harness advanced sub 3nm fabrication nodes and integrated silicon photonics for its upcoming generation of custom ASICs.
Expanding Custom Silicon Portfolio
Marvell aims to expand its custom silicon portfolio by leveraging TSMC’s most sophisticated process technologies.
Following its March announcement of 2nm silicon IP for AI, cloud infrastructure, and networking applications, the company is now reportedly preparing to utilize even more refined sub 3nm nodes.
In parallel, it plans to integrate TSMC’s silicon photonics technology, enabling faster optical I/O and a more than tenfold boost in signal transmission speed.
Strategic Momentum in the ASIC Landscape
Marvell has built a strong position in the ASIC segment through strategic partnerships. Its first major custom chip deal was with AWS in 2021, followed by a design engagement with Meta in late 2024.
During its AI Investor Day in June 2025, Marvell revealed that custom ASICs already made up over 25% of its Q4 FY25 data center revenue, with projections that this figure will surpass 50% in upcoming quarters.
Simultaneously, major hyperscalers such as Google, AWS, Microsoft, and Meta are aggressively expanding their in-house custom chip efforts.
Examples include Google’s TPU v6, AWS’s Trainium v2 developed with Marvell, Meta’s MTIA v2 in collaboration with Broadcom, and Microsoft’s Maia v2 chip co-developed with Marvell.
The Platform Play: IP Rich and Vertically Integrated
Marvell’s approach centers on developing a comprehensive IP platform for custom silicon. This includes SerDes interfaces, custom SRAM, HBM memory architecture, silicon photonics, die-to-die interconnects, high-performance SoC fabrics, and advanced packaging technologies.
These elements allow Marvell to tailor ASIC solutions specifically for AI, networking, storage, and hyperscale data centers.
The partnership with TSMC spans several technology generations—from 5nm and 3nm to the latest 2nm nodes—allowing Marvell to deliver highly efficient, scalable silicon architectures.
Why It Matters
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Performance at scale: Sub 3nm nodes and silicon photonics offer massive gains in bandwidth, energy efficiency, and signal latency reduction.
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AI-driven differentiation: These innovations enable Marvell to support custom AI accelerators that power future data centers.
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Competitive positioning: With tech giants developing proprietary ASICs, Marvell’s advanced design capabilities are critical to securing long-term client relationships.
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Integrated innovation: A rich stack of reusable IP blocks sets Marvell apart from design firms with narrower technology scopes.
Looking Ahead
Marvell’s reported move into sub 3nm and photonics-powered ASICs signals a doubling down on its platform-driven strategy. Building atop its recent 2nm silicon IP milestone, the company is betting on deeper process scaling and optical data transport to lead the next generation of custom chip deployments.
As more cloud and AI workloads demand customized architectures, Marvell’s emphasis on high-performance design, modularity, and integration may be the formula that secures its position among the industry’s top ASIC players.
Summary at a Glance
| Topic | Key Insight |
|---|---|
| Technology upgrade | Marvell is progressing beyond 2nm to TSMC’s sub 3nm node and adopting silicon photonics. |
| Client growth | AWS, Meta, Microsoft, and others play key roles in its custom chip business. |
| Revenue signal | Custom ASICs now account for over 25% of data center revenue and growing. |
| Strategic advantage | Marvell’s vertically integrated IP stack provides flexibility and scalability. |
