Following the successful evaluation of test chips in both 180 nm and 22 nm process nodes, sureCore recently announced the launch of a range of cryogenic IP. The company also disclosed that it has partnered with packaging experts Sarcina, who created a unique package for cryogenic temperatures.
Innovate UK project background
The partnership, which was sponsored by the IUK, consists of a full ecosystem of companies with the fundamental skills and knowledge needed to create cryo-tolerant semiconductor IP.
The project’s goal is to develop and prove a set of foundational IP that designers can license to develop their own Cryo-CMOS SoC solutions. Their competitive advantage in the field of quantum computing will be significantly increased if they achieve this.
Utilizing its cutting-edge, ultra-low power memory design expertise, sureCore has developed embedded Static Random Access Memory (SRAM), a crucial component of any digital subsystem, that can function at temperatures as low as 77K (-196°C) or as high as the near-zero temperatures required by Quantum Computers (QCs).
An industry-standard RTL to GDSII physical design path may now be easily adopted because both standard cell and IO cell libraries have been re-characterized for operation at cryogenic temperatures.
The ability to collocate ever-more complex control electronics near the qubits that need to be kept in a cryostat at cryogenic temperatures is a major obstacle to QC scalability.
This requires that the power consumption of the control chip be kept as low as possible in order to minimize extra heat and prevent the cryostat from experiencing additional thermal load. SureCore’s knowledge in low power design was crucial in this situation.
Since modern semiconductor technology can only function at temperatures as low as -40°C, the control electronics in current QC systems are situated outside the cryostat. The transistors’ working characteristics significantly alter as the temperature is lowered toward absolute zero.
The possibility of creating interface devices that can regulate and observe qubits at cryogenic temperatures is demonstrated by the measurement, comprehension, and modeling of this behavioral shift during the previous several months.
The qubits housed in the cryostat are currently connected to room temperature control devices via costly, cumbersome wiring.
A game-changer that will quickly enable QC scaling is allowing QC developers to take use of the fabless design paradigm and construct their own unique cryogenic control SoCs that can be housed alongside the qubits within the cryostat. Cost, size, and—most importantly—latency reduction are immediate advantages.
The demonstrator chip will then be characterized at cryotemperatures in order to further hone and validate the models and enhance performance.
Key Comments
Paul Wells, sureCore’s CEO, explained, “This represents another critical step in our programme to make Cryo-CMOS available for the Quantum Computing (QC) ecosystem. Our CryoMem™ range of memory IP is silicon proven in addition to validating our library recharacterization service. We are also offering a range of cryogenic design capabilities to help QC companies design the control/interface chips which need to be migrated into the cryostat alongside the qubits. Reliable, robust, cryo-ready chip packaging is a necessity in these harsh, low temperature environments and to ensure this we partnered with Sarcina whose specialist package design expertise is second to none.”
Larry Zu, Sarcina’s CEO, added, “We have developed a reputation as the “go-to” design expert for companies needing to push the boundaries of current packaging technology. Whether this be for complex multi-chip 3D solutions, or, as in this case, for extreme low temperature operation, our experience and know-how allowed us to develop a custom BGA package specially for cryogenic temperatures.”
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