Cadence Design Systems has declared that its first Arm-based system chiplet has been developed and successfully taped out. The company describes this as a major advancement since it has successfully designed, prototyped, and taped out the first system chiplet in the industry.
This chiplet combines processors, memory IP, and system IP into a single package and is connected via the Universal Chiplet Interconnect Express (UCIe) standard interface.
The chiplet was created in collaboration with Arm and conforms to Arm’s Chiplet System Architecture (CSA), a standard that guarantees interoperability and expedites chiplet time-to-market.
A system chiplet comprises components such a system processor, safety management processor, Cadence controllers, and Cadence PHY IP for LPDDR5 and UCIe, and it has the ability to control the resources and functionality of the entire multi-chiplet SoC. The chiplet, which uses Cadence Janus NoC technology, can support a maximum bandwidth of 64GB/s for UCIe IP and 32GB/s for LPDDR5 IP.
Cadence Design Systems and Arm formally announced their long-standing partnership earlier this year in order to provide a state-of-the-art software development platform and a chiplet-based reference design. Through this collaboration, Arm’s cutting-edge IP technologies are combined with Cadence’s IP and EDA solutions, greatly lowering design complexity and speeding up time-to-market for clients.
More developments between the two businesses are anticipated, with the goal of providing clients with a whole development platform that offers improved effectiveness and performance.
Investing in the Arm CSA is the pivotal strategy for this partnership since it allows suppliers to reuse more components. Cadence is creating chiplets that adhere to this standard and actively participates in the CSA. Chiplets like Arm Compute Subsystems (CSS) and the Cadence Design Systems chiplet can scale and reach the market more quickly thanks to these standards.
Customers can launch innovations faster by abstracting functionality into chiplet IP. The demand for improved design efficiency, quicker platform refresh cycles, and optimized power, performance, and area (PPA) metrics is driving the transition from monolithic SoCs to chiplet-based designs.
Chiplets integrate cross-foundry process technologies into a single package, enabling a multi-foundry business model.